Car controlling unit using a multitasking system

ABSTRACT

The present invention provides a multi-task system which can suppress the increase of required volume of RAM and which enables a multiplex interruption, and a car controlling unit utilizing that system. A memory area (RAM) utilized in executing a processing is divided into a task area  50  for carrying out a task processing and an interrupt area  60  for carrying out an interrupt processing. An interrupt level is given to the interrupt processing in accordance with its priority. The interrupt area is prepared so that the number thereof is same as that of the interrupt level. This system can suppress the increase of memory areas to be consumed as the interrupt area and can guarantee that all interrupt processings are operated.

TECHNICAL FIELD

The present invention relates to a technology for managing a memory of acomputer unit and more specifically to a technology for managing amemory of a computer unit such as a car controlling unit whose memorycapacity is limited.

BACKGROUND ARTS

A stack area 300 used by each task is reserved on RAM (Random AccessMemory) per each task in a multi-task system, which processes aplurality of tasks concurrently on a computer. As shown in FIG. 5(a), atask program and an interrupt program use there served stack area 300 ingeneral. Then, when interrupt processing occurs while executingprocessing of a task 1, for example, the interrupt processing utilizesan area not used by the task program in the stack area 300 for the task1. Considered from the nature of the interrupt processing, it isrequired to operate reliably at any time whenever it occurs. Therefore,the task area 300 has to reserve a capacity, which enables to operate atask processing, and a capacity that enables to operate all theinterrupt processing per task.

Accordingly, when a number of tasks increases, the RAM utilizationefficiency drops, while the capacity of the RAM to be reservedincreases. This is not a big problem for a computer with a plenty ofmemory. However, the above-mentioned problem is serious for a carcontrolling unit, which is mounted on a car, because the capacity of theRAM is limited.

Japanese Patent Laid-Open No. Hei. 123698/1996 has disclosed, as shownin FIG. 5(b), a technology of reserving in a stack area only a task area301 per task and only one interrupt area 303 in common to all tasks.This technology enables to suppress the increase of required amount ofthe RAM because it is only the task area that is to be reserved anew andthe interrupt area is utilized in common, even when the number of tasksincreases.

DISCLOSURE OF THE INVENTION

However, when multiplex interruption is considered, this technologyrequires reserving areas corresponding to the maximum number ofinterruptions, which may occur concurrently. Therefore, the requiredamount of the RAM cannot be reduced.

In view of the circumstances described above, it is an object of thepresent invention to provide a car controlling unit that allows amultiple interrupt processing, where the increase of required amount ofRAM can be suppressed.

In order to achieve the above-mentioned object, a car controlling unitcomprises, interrupt request issuing means for issuing an interruptrequest which is associated with one of a plurality of interrupt levelswhich indicates a priority of interrupt processing; an interruptcontroller which receives the interrupt request and decides whether ornot to allow the interrupt request based on the interrupt levelassociated with the interrupt request thus received; a centralprocessing unit which executes a task processing and an interruptprocessing, and when an interrupt request is allowed, the centralprocessing unit temporarily suspends the task processing or theinterrupt processing to execute the interrupt processing whose interruptrequest has been allowed; and a memory having a plurality of task areasutilized as a stack by the task processing and a plurality of interruptareas utilized as a stack by the interrupt processing, wherein, thenumber of the interrupt areas is equal to the number of the interruptlevels, and the central processing unit utilizes any one of the taskareas as a stack in executing each of the task processings, and utilizesany one of the interrupt areas as a stack in executing the interruptprocessing whose interrupt request has been allowed.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagram showing a functional structure of a car controllingunit to which the present invention may be applied;

FIG. 2 is a diagram showing a state of use of the memory of the presentinvention;

FIG. 3 is a transition diagram of a state of use of the memory of thepresent invention;

FIG. 4 is a flowchart explaining a memory managing method of the presentinvention; and

FIG. 5 is a diagram showing a state of use of a memory in the prior art.

BEST MODE FOR CARRYING OUT THE INVENTION

In controlling a car, an appropriate control is required according to astate of a car that changes every moment. Therefore, it is difficult tomonitor by a CPU (Central Processing Unit) all of the states whichcontinue to change. Then, a plurality of controllers respectivelymonitor their assigned ranges, and notify the change of state to the CPUin a form of interrupt. A CPU time for carrying out a requiredprocessing is assigned to each controller. Generally, the number ofinterrupts, which may occur in the car controlling unit, is about 5 to20. In such a system with a large number of interrupts and theoccurrence thereof is frequent, exhaustion of memory may be serious ifinterrupt areas corresponding to the number of interrupts are reservedas done in conventional arts. Accordingly, it is very effective to applythe present invention to the car controlling unit.

An embodiment of the present invention applied to the car controllingunit will be explained with reference to the drawings.

A car control unit 1 is composed as a set of a plurality of controlunits as shown in FIG. 1. It comprises per control unit at least a CPU,a ROM (Read Only Memory), a RAM and an interrupt controller. An engineand transmission control unit 1 will be exemplified here, but it is alsopossible to conduct a similar memory management in other control unitssuch as a brake control unit 20 and a suspension control unit 30.

The engine and transmission control unit 1 comprises, for example, asshown in FIG. 1, a CPU 11, a ROM 12, a RAM 13, an interrupt controller14, a timer 15, a pulse meter 16, an AD converter 17, and acommunication interface 18.

The CPU 11 executes an information processing in accordance to aprogram. The RAM 12 stores programs for a task processing and aninterrupt processing executed by the CPU 11.

The task processing includes a task for performing a control notsynchronized with engine revolutions and a task for carrying out aprocess for controlling the engine revolutions. More preferably, thenon-synchronizing task may include a task for performing a process,which requires no synchronization with the engine revolutions or a taskfor carrying out a computation of parameters not influenced by theengine revolutions. These are started up by an interrupt request thatoccurs at constant period like a timer interrupt. Engine control tasksmay include a task for controlling the engine revolutions such as anignition-computing task for carrying out at least one of the calculatingprocesses of engine ignition timing, fuel injection amount and injectiontiming. Beside those mentioned above, there are tasks such as concerninga car attitude control and concerning a transmission control.

The interrupt processing may include, for example, a periodic interruptprocessing for carrying out a processing at constant intervals, and aninterrupt processing for performing a control in accordance with a stateof the engine. Preferably, there may be an interrupt processing, wherethe periodic interrupt processing is started up upon receipt of aninterrupt request at constant intervals, a task is started up atconstant period, or a time management is conducted. The interruptprocessing for performing a control in accordance with the state ofengine may include an engine rotation angle interrupt processing forcarrying out a computing processing of parameters to be controlled inaccordance with the engine rotation angle. Besides those mentionedabove, there are interrupt processings such as concerning a car attitudecontrol and concerning a transmission control, and a timer interruptprocessing.

The RAM 13 includes a stack area utilized by each task processing andinterrupt processing as a stack, and a variable area, etc. Theconstruction of the stack area of the RAM 13 and its utilization will bedescribed in detail later.

The interrupt controller 14 performs an interrupt control to the CPU 11,after a receipt of an interrupt inputted from the followings, i.e., atimer 15 which is a time measuring mechanism, a pulse meter 16 whichreceives a pulse from a pulse generator (not shown) and measure thepulse, the pulse generator monitoring a state of each part constitutinga car and generating a pulse outputs, an AD converter 17 which receivesan analogue output from a sensor (not shown) which monitors theaforementioned state of each part, and a communication interface 18which communicates with other control units. The interrupt controller 14is adaptable for multiplex interruption for receiving a plurality ofinterrupts concurrently. Further, an interrupt level is set in theinterrupt controller 14 corresponding to a priority of interruptprocessing. Here, three levels from Level 1 to Level 3 are set as theinterrupt level. It is indicated that the greater the number of theinterrupt level, the higher the priority is. When an interrupt requestwith an interrupt level higher than that of the interrupt processingbeing executed is made, the interrupt controller 14 allows the CPU 11 toexecute the interrupting processing with a higher priority of interruptlevel by suspending the interrupt processing being executed.

The interrupt level may be set as the following for example. A priorityof the interrupt processing for a control in accordance with the stateof the engine described above is normally higher than that of theabove-mentioned periodic interrupt processings. Therefore, the interruptlevel of the interrupt processing relating to the engine control is madehigher. In the concrete, the interrupt level of the timer interruptprocessing which receives interrupt requests at a constant interval maybe set as 1 and the engine rotation angle interrupt processing may beset as 3.

The timer 15 generates a timer interrupt every constant period of time.The pulse meter 16 receives a pulse generated by the pulse generator notshown. The pulse generator generates a pulse corresponding to a rotationangle of a rotary member whose rotation angle and rotation speed need tobe controlled. For example, the pulse generator is mounted on a crank ofan engine or a gear of a transmission to generate the pulsecorresponding to its crank angle or gear angle. Then, the pulse meter 16requests a predetermined interrupt processing to the interruptcontroller 14 in response to the pulse thus received. The AD converter17 monitors the state of each part constituting the car and receives ameasured value of a sensor, not shown, which outputs an analog output.For instance, the AD converter 17 receives measured values from a watertemperature sensor of the engine and an oil temperature sensor of thetransmission, etc. Then, the AD converter 17 requests a predeterminedinterrupt processing to the interrupt controller when the sensorcompletes the measurements. The AD converter 17 may also request aninterrupt processing in accordance with types and values of the measuredvalues thus received. An interrupt request from other control units suchas a brake control unit 20 is inputted to the interrupt controller 14via the communication interface 18.

Next, a memory structure of the present embodiment will be explained.

FIG. 2 diagrammatically shows a state of use of the stack area of theRAM 13 in executing a task. FIG. 2(a) shows the structure of a task area50, which is a stack area used by the task. The number of tasks isdetermined in advance and the task areas 50 corresponding to the numberof tasks are reserved. Each task utilizes as a stack area the task area50 that is allocated to each own task. FIG. 2(a) shows a state in whichthere exist three tasks. Here, it is indicated that an address 51 ofeach task area 50 (50 a, 50 b, 50 c) is set as 1001 to 1100 for the areaof the task 1, 2001 to 2100 for the area of the task 2 and 3001 to 3100for the area of the task 3. 1100, 2100 and 3100 are called as a baseaddress 51 a of the memory area for each task.

FIG. 2(b) shows a structure of an interrupt area 60, which is a stackarea used by an interrupt processing. The number of interrupt areas 60being reserved is same as that of the interrupt level. Here, since thereare three interrupt levels, there are three interrupt areas (60 a, 60 b,60 c). The base addresses 61 a of the interrupt areas 60 are 130, 230and 330, respectively.

The number of interrupt areas 60 is set equal to the number of interruptlevels by the following reasons. That is, when a different interruptprocessing occurs while one interrupt processing is being carried out,the interrupt controller 14 allows the interrupt processing which occurslater to be executed only when the level of interrupt processing whichoccurs later is higher than the interrupt level of the interruptprocessing currently being executed. When the interrupt level of theprocessing occurs later is equal to or lower than the interrupt level ofthe processing being executed, the interrupt controller 14 causes thatprocessing to wait until when the interrupt processing being executedends. Accordingly, in the multiplex interrupt system provided withinterrupt levels, the maximum number of the interrupt processings thatmay occur concurrently is equal to the number of interrupt levels.Accordingly, a normal operation is guaranteed, even though an interruptprocessing occurs in any case and at any time, just by reserving theinterrupt areas 60 the number of which corresponds to the number ofinterrupt levels.

Next, a manner of transition in the state of using a memory will beexplained referring to FIGS. 3 and 4.

FIG. 3(a) shows a state in which there are three tasks, and the task 2is being executed. At this time, no interrupt processing is occurring.Accordingly, none of the interrupt areas 60 are used.

FIG. 3(b) shows the state in which an interrupt processing A with theinterrupt level 1 occurs while the task 2 is being executed as shown inFIG. 3(a). FIG. 4 shows a procedure of memory management for this case.That is, when the interrupt controller 14 allows the interrupt, theprocessing of the task 2 being executed at that point of time issuspended. Then, a program counter 70 (PC) at that point of time issaved in the task area 50 b for the task 2 (Step 110). The CPU 11 oncesaves the present contents (2040) of a stack pointer, not shown, in aregister, not shown, then, switches the stack pointer by setting thebase address 61 a (130) of the interrupt area 60 a to the stack pointer.Then, the CPU 11 stores the contents (2040) corresponding to the stackpointer having been saved in the register, into the interrupt area 60 afor the interrupt level 1 (Step 120). After that, the CPU11 saves thecontents of the register, which has been used by the task 2, to theinterrupt area 60 a (Step 130). Then, the interrupt processing A isexecuted (Step 140).

Here, assume that an interrupt processing B with the interrupt level 3further occurs while the interrupt processing A is being executed. Atthis time, the interrupt processing B is allowed to be executed becauseits priority is higher than that of the interrupt processing A. Then,the CPU 11 suspends the interrupt processing A, saves the programcounter 70 (PC) at this time (Step 110), saves the contents (108) of thestack pointer for switching (Step 120), and saves the contents of theregister to the interrupt area 60 c for the interrupt level 3 (Step130). Then, the interrupt processing B is executed (Step 140). FIG. 3(c)shows a using state of the RAM 12 at this time.

When the interrupt processing B ends, the CPU 11 restores the contentsof the register from the interrupt area 60 c (Step 150). It thenrestores the stack pointer, which has been saved to the interrupt area60 c, and performs switching (Step 160). It restores the program counter(Step 170) and resumes the interrupt processing A which has beensuspended. FIG. 3(b) shows the using state of the RAM 12.

Then, when the interrupt processing A ends, the CPU 11 restores thecontents of the register from the interrupt area 60 a (Step 150) andrestores and switches the stack pointer (Step 160). After that, the CPU11 restores the program counter (Step 170) and resumes to process theprocessing that has been suspended, i.e. the task 2. FIG. 3(a) shows theusing state of the RAM 12 at this time.

As described above, a normal processing is guaranteed against anyinterruption by reserving interrupt areas the number of whichcorresponds to the number of the interrupt levels. That is, since it isnot necessary to reserve the interrupt areas corresponding to allinterrupt processings as disclosed in the conventional art, the increaseof the required volume of the RAM may be suppressed. This isparticularly significant for the car controlling unit.

As described above, according to the present invention, it is possibleto provide a car controlling unit, which can suppress the increase ofrequired volume of RAM, and enables multiplex interrupt processings.

What is claimed is:
 1. A car controlling unit, comprising: interruptrequest issuing means for issuing an interrupt request being associatedwith one of a plurality of interrupt levels, which indicates a priorityof an interrupt processing; an interrupt controller which receives saidinterrupt request and decides whether or not said interrupt request isallowed, based on the interrupt level associated with said interruptrequest thus received; a central processing unit which executes a taskprocessing and an interrupt processing, and which suspends the taskprocessing or the interrupt processing being executed when saidinterrupt request has been allowed, so as to execute said interruptprocessing whose interrupt request has been allowed; and a memory havinga plurality of task areas to be used as a stack by said task processingand a plurality of interrupt areas to be used as a stack by interruptprocessing, wherein, a number of said interrupt areas is equal to anumber of said interrupt levels; said central processing unit utilizesany one of said task areas as a stack in executing each of said taskprocessing; and said central processing unit utilizes any one of saidinterrupt areas as a stack in executing said interrupt processing whoseinterrupt request has been allowed.
 2. The car controlling unitaccording to claim 1, further comprising, monitoring means formonitoring a state of a car, wherein, said interrupt request issuingmeans issues said interrupt request based on a result of monitoring bysaid monitoring means.
 3. The car controlling unit according to claim 2,wherein said monitoring means is a pulse generator which generates apulse corresponding to a rotation angle of a rotary member whoserotation angle or rotation speed is to be controlled; and said interruptrequest issuing means is a pulse meter which receives the pulse fromsaid pulse generator and issues the interrupt request in accordance withthe pulse thus received.
 4. The car controlling unit according to claim2, wherein said monitoring device is a sensor which measures the stateof the car and outputs measured values in analog; and said interruptrequest issuing means is an AD converter which receives the measuredvalues from said sensor and issues the interrupt request when ameasurement of said sensor is completed.
 5. The car controlling unitaccording to claim 1, wherein said interrupt request issuing means is atimer.
 6. The car controlling unit according to claim 1, furthercomprising a communication interface for communicating with other carcontrolling unit, wherein, said interrupt request issuing means issuesthe interrupt request to said communication interface; and saidinterrupt controller receives the interrupt request from saidcommunication interface.
 7. A car controlling unit, comprising: a pulsegenerator that generates a pulse corresponding to a rotation angle of anengine; a pulse meter that receives the pulse from said pulse generator,measures a number of the pulse thus received and issues an interruptrequest corresponding to a result of the measurement; a timer forgenerating an interrupt request at a predetermined time interval;interrupt processing means comprising engine rotation angle interruptprocessing means being associated with the interrupt request generatedby said pulse meter, and timer interrupt processing means beingassociated with the interrupt request generated by said timer; and amemory having a plurality of interrupt areas to be utilized as a stackby said interrupt processing means; wherein the interrupt requestgenerated by said pulse meter and the interrupt request generated bysaid timer are associated with one of a plurality of interrupt levels,respectively, which indicate a priority of an interrupt processing, andthe interrupt request generated by said pulse meter and the interruptrequest generated by said timer are associated with the interrupt levelswhose priority are different from each other, and wherein, each of saidinterrupt areas is associated with any one of said plurality ofinterrupt levels in one-to-one correspondence; said rotation angleinterrupt processing means utilizes as a stack said interrupt area whichis associated with the interrupt level in one-to-one correspondence,that interrupt level being associated with said rotation angle ofinterrupt processing means; and said timer interrupt processing meansutilizes as a stack said interrupt area which is associated with theinterrupt level in one-to-one correspondence, that interrupt level beingassociated with said timer interrupt processing.